A flash memory is widely used as a type of EEPROM (Electrically Erasable and Programmable Read Only Memory), which is an electrically writable/erasable non-volatile semiconductor storage device. The flash memory has an electrically-conductive floating gate electrode surrounded by an oxide film or a trap insulating film below a gate electrode of a MISFET. Information is stored by utilizing the difference in the threshold value of the MISFET depending on presence/absence of charge (electrons or holes) in the floating gate or the trap insulating film.
For example, Japanese Patent Application Laid-Open Publication No. 2005-123518 (Patent Document 1) discloses a non-volatile memory cell in which a charge retaining characteristic is improved by providing a taper on a sidewall of a select gate electrode (15) in order to improve the charge retaining characteristic by suppressing reduction in the thickness of a corner part (20) of a charge accumulating film. For example, paragraphs [0041] and [0042] disclose that a sidewall spacer (69) of a silicon oxide film is formed after the formation of the select gate electrode, thereby controlling the angle of a corner part of an ONO-film (FIG. 25).
Japanese Patent Application Laid-Open Publication No. 2001-148434 (Patent Document 2) discloses a non-volatile memory cell capable of achieving the low-voltage drive, high-speed program, and high-density integration. In this disclosure, for example, in order to reduce the coupling capacitance between a first gate electrode (141) and a second gate electrode (142) to improve a driving speed, an end surface of a gate electrode (141) is oxidized to form an oxide film (141a) or a sidewall (not shown) serving as an insulating member is formed on a side surface of the gate electrode (141) instead of the oxide film (141a) (paragraph [0108], FIG. 13). It also discloses that the capacitance between gate electrodes is reduced by oxidizing an end surface of a gate electrode (241) to form an oxide film (241a) or forming a sidewall serving as an insulating member on a side surface of the gate electrode (241) instead of the oxide film (241a) (paragraph [0128], FIG. 18).
Japanese Patent Application Laid-Open Publication No. 2010-108976 (Patent Document 3) discloses a semiconductor device in which a corner part, which is formed at an end part of a side in contact with a gate insulating film (GOX), is processed into a reversely tapered shape at a control gate electrode (CG) of a memory cell, thereby suppressing the disturbance. It also discloses that the distance between the control gate electrode (CG) and the memory gate electrode (MG) is increased in a region close to a semiconductor substrate by increasing the film thickness (film thickness b) of a potential barrier film (EV1) at a lower part of the control gate electrode (CG), thereby suppressing the disturbance (paragraphs [0105] to [0108], FIG. 14, FIG. 15).
Japanese Patent Application Laid-Open Publication No. 2011-103401 (Patent Document 4) discloses a split-gate-type memory cell in which a sidewall insulating film (11) composed of, for example, a silicon oxide film or a silicon nitride film is formed between a stacked gate insulating film (9) and a memory gate electrode (10) which are formed on one of sidewalls of a control gate electrode (8), and the memory gate electrode is electrically separated from the control gate electrode by the sidewall insulating film and the stacked gate insulating film. This structure can prevent the short-circuit failure caused by contact between a silicide layer formed on the surface of the control gate electrode and a silicide layer formed on the surface of the memory gate electrode. The inside of parentheses shows symbols described in the documents.